View M58LR128KT705_7735758.PDF datasheet online --- IC-ON-LINE

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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. march 2008 rev 3 1/111 1 m58lr128kt m58lr128kb m58lr256kt m58lr256kb 128 or 256 mbit (16, multiple bank, multilevel interface, burst) 1.8 v supply flash memories features supply voltage ?v dd = 1.7 v to 2.0 v for program, erase and read ?v ddq = 1.7 v to 2.0 v for i/o buffers ?v pp = 9 v for fast program synchronous/asynchronous read ? synchronous burst read mode: 54 mhz, 66 mhz ? asynchronous page read mode ? random access: 70 ns, 85 ns synchronous burst read suspend programming time ? 2.5 s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 8 mbit banks for the m58lr128kt/b 16 mbit banks for the m58lr256kt/b ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp for block lock-down ? absolute write protection with v pp = v ss security ? 64 bit unique device number ? 2112 bit user programmable otp cells common flash interface (cfi) 100 000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? top device codes: m58lr128kt: 88c4h m58lr256kt: 880dh ? bottom device codes m58lr128kb: 88c5h m58lr256kb: 880eh the m58lrxxxkt/b memories are only available as part of a multichip package. not packaged separately www.numonyx.com
contents m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 2/110 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 address inputs (a0-amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 data inputs/outputs (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 reset (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.9 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.14 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.15 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb contents 3/110 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 blank check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . 24 4.10.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10.2 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10.3 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.12 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.14 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.15 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.16 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.17 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 erase/blank check status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.7 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.8 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . 36 6 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 x latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.4 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.5 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
contents m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 4/110 6.7 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.9 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2.1 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.3 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 49 9 block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.1 reading block lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.3 unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.4 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.5 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 52 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 54 11 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 appendix c flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 appendix d command interface state ta bles. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb list of tables 5/110 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. m58lr128kt/b bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. m58lr256kt/b bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9. protection register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 11. x latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 12. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 13. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 14. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 15. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 17. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 18. program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 22. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 23. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 24. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 25. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 26. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 27. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 29. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 30. m58lr128kt - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 31. m58lr128kt - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 32. m58lr128kt - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 33. m58lr256kt - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 34. m58lr256kt - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 35. m58lr256kt - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 36. m58lr128kb - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 37. m58lr128kb - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 38. m58lr128kb - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 39. m58lr256kb - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 40. m58lr256kb - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 41. m58lr256kb - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 42. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 43. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 44. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 table 45. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 46. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 47. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 48. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
list of tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 6/110 table 49. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 50. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 51. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 52. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 53. command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 103 table 54. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 55. command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 107 table 56. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb list of figures 7/110 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. m58lr128kt/b memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. m58lr256kt/b memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5. x latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 10. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 12. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 13. synchronous burst read suspend ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 14. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 15. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 16. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 17. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 18. program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 figure 19. blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 20. buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 21. program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 22. block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 23. erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 24. locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 25. protection register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 26. buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . 99
description m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 8/111 1 description the m58lr128kt/b and m58lr256kt/b are 128 mbit (8 mbit 16) and 256 mbit (16 mbit 16) non-volatile flash memories, respectively. they can be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 v to 2.0 v v dd supply for the circuitry and a 1.7 v to 2.0 v v ddq supply for the input/output pins. an optional 9 v v pp power supply is provided to accelerate factory programming. the devices feature an asymmetrical block architecture: the m58lr128kt/b have an array of 131 blocks, and are divided into 8 mbit banks. there are 15 banks each containing 8 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 7 main blocks of 64 kwords. the m58lr256kt/b have an array of 259 blocks, and are divided into 16 mbit banks. there are 15 banks each containing 16 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 15 main blocks of 64 kwords. the multiple bank architecture allows dual operations. while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in ta bl e 2 , and the memory map is shown in figure 2 . the parameter blocks are located at the top of the memory address space for the m58lr128kt and m58lr256kt, and at the bottom for the m58lr128kb and m58lr256kb. each block can be erased separately. erase can be suspended to perform a program or read operation in any other block, and then resumed. program can be suspended to read data at any memory location except for the one being programmed, and then resumed. each block can be programmed and erased over 100 000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller manages the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 mhz. the synchronous burst read operation can be suspended and resumed. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. the m58lrxxxkt/b features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power-up.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb description 9/111 the device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 one-time-programmable (otp) protection registers of 128 bits each. the first protection register is divided into two segments: a 64 bit segment containing a unique device number written by numonyx, and a 64 bit segment otp by the user. the user programmable segment can be permanently protected. figure 4 , shows the protection register memory map. the m58lrxxxkt/b are only available as part of a multichip package. the devices are supplied with all the bits erased (set to ?1?).
description m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 10/111 figure 1. logic diagram 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. table 1. signal names signal name function direction a0-amax (1) 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. address inputs inputs dq0-dq15 data input/outputs, command inputs i/o e chip enable input g output enable input w write enable input rp reset input wp write protect input k clock input l latch enable input wait wait output v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply ai14011 a0-amax (1) w dq0-dq15 v dd m58lr128kt m58lr128kb m58lr256kt m58lr256kb e v ss 16 g rp wp v ddq v pp l k wait v ssq
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb description 11/111 figure 2. m58lr128k t/b memory map table 2. m58lr128kt/b bank architecture number bank size parameter blocks main blocks parameter bank 8 mbits 4 blocks of 16 kwords 7 blocks of 64 kwords bank 1 8 mbits - 8 blocks of 64 kwords bank 2 8 mbits - 8 blocks of 64 kwords bank 3 8 mbits - 8 blocks of 64 kwords ---- ---- ---- ---- bank 14 8 mbits - 8 blocks of 64 kwords bank 15 8 mbits - 8 blocks of 64 kwords ai14012 m58lr128kt - top boot block address lines a0-a22 8 main blocks bank 15 m58lr128kb - bottom boot block address lines a0-a22 64 kword 000000h 00ffffh 64 kword 070000h 07ffffh 64 kword 600000h 60ffffh 64 kword 670000h 67ffffh 64 kword 680000h 68ffffh 64 kword 6f0000h 6fffffh 64 kword 700000h 70ffffh 64 kword 770000h 77ffffh 64 kword 780000h 78ffffh 64 kword 7e0000h 7effffh 16 kword 7f0000h 7f3fffh 16 kword 7fc000h 7fffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 070000h 07ffffh 64 kword 080000h 08ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 170000h 17ffffh 64 kword 180000h 18ffffh 64 kword 1f0000h 1fffffh 64 kword 780000h 78ffffh 64 kword 7f0000h 7fffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 4 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
description m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 12/111 figure 3. m58lr256k t/b memory map table 3. m58lr256kt/b bank architecture number bank size parameter blocks main blocks parameter bank 16 mbits 4 blocks of 16 kwords 15 blocks of 64 kwords bank 1 16 mbits - 16 blocks of 64 kwords bank 2 16 mbits - 16 blocks of 64 kwords bank 3 16 mbits - 16 blocks of 64 kwords ---- ---- ---- ---- bank 14 16 mbits - 16 blocks of 64 kwords bank 15 16 mbits - 16 blocks of 64 kwords ai14013 m58lr256kt - top boot block address lines a23-a0 16 main blocks bank 15 m58lr256kb - bottom boot block address lines a23-a0 64 kword 000000h 00ffffh 64 kword 0f0000h 0fffffh 64 kword c00000h c0ffffh 64 kword cf0000h cfffffh 64 kword d00000h d0ffffh 64 kword df0000h dfffffh 64 kword e00000h e0ffffh 64 kword ef0000h efffffh 64 kword f00000h f0ffffh 64 kword fe0000h feffffh 16 kword ff0000h ff3fffh 16 kword ffc000h ffffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 1f0000h 1fffffh 64 kword 200000h 20ffffh 64 kword 2f0000h 2fffffh 64 kword 300000h 30ffffh 64 kword 3f0000h 3fffffh 64 kword f00000h f0ffffh 64 kword ff0000h ffffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 16 main blocks 16 main blocks 16 main blocks 15 main blocks 4 parameter blocks 15 main blocks 16 main blocks 16 main blocks 16 main blocks 16 main blocks
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb signal descriptions 13/111 2 signal descriptions see figure 1: logic diagram and table 1: signal names for a brief overview of the signals connected to this device. 2.1 address inputs (a0-amax) amax is the highest order address input. it is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 output enable (g ) the output enable input controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable input controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first. 2.6 write protect (wp ) write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to table 17: lock status ).
signal descriptions m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 14/111 2.7 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 22: dc characteristics - currents for the value of i dd2. after reset all blocks are in the locked state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, and a negative transition of chip enable or latch enable is required to ensure valid data outputs. 2.8 latch enable (l ) latch enable latches the address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . 2.9 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.10 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih , output enable is at v ih or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. 2.11 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.12 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb signal descriptions 15/111 2.13 v pp program supply voltage v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a voltage lower than v pplk provides absolute protection against program or erase, while v pp in the v pp1 range enables these functions (see tables 22 and 23 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase. a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. 2.14 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.15 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1 f ceramic capacitor close to the pin (high frequency, inhere ntly low inductance capacitors should be as close as possible to the package). see figure 8: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
bus operations m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 16/111 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby and reset. see table 4: bus operations for a summary. typically glitches of less than 5 ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations are used to output the c ontents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il to perform a read operation. the chip enable input should be used to enable the device, and output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 9 , 10 and 11 read ac waveforms, and tables 24 and 25 read ac characteristics for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses must be latched prior to the write operation by toggling latch enable (when chip enable is at v il ). the latch enable must be tied to v ih during the bus write operation. see figures 15 and 16 , write ac waveforms, and tables 26 and 27 , write ac characteristics for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih .
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb bus operations 17/111 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level i dd3 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. 3.6 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the reset level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 4. bus operations (1) 1. x = ?don't care? operation e g w l rp wait (2) 2. wait signal polarity is configured us ing the set configuration register command. dq15-dq0 bus read v il v il v ih v il (3) 3. l can be tied to v ih if the valid address has been previously latched. v ih data output bus write v il v ih v il v il (3) v ih data input address latch v il xv ih v il v ih data output or hi-z (4) 4. depends on g . output disable v il v ih v ih xv ih hi-z hi-z standby v ih xxxv ih hi-z hi-z reset x x x x v il hi-z hi-z
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 18/111 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller manages all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands are ignored. refer to table 5: command codes , table 6: standard commands , ta bl e 7 : fa c t o r y commands and appendix d: command interface state tables for a summary of the command interface. table 5. command codes hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 40h program setup 50h clear status register 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 80h buffer enhanced factory program setup 90h read electronic signature 98h read cfi query b0h program/erase suspend bch blank check setup c0h protection register program cbh blank check confirm d0h program/erase resume, block erase confirm, block unlock confirm, buffer program or buffer enhanced factory program confirm e8h buffer program ffh read array
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 19/111 4.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command. once a bank is in read array mode, subsequent read operations outputs the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues, however the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. 4.2 read status register command the device contains a status register that monitors program or erase operations. the read status register command reads the contents of the status register for the addressed bank. one bus write cycle is required to issue the r ead status register command. once a bank is in read status register mode, subsequent read operations output the contents of the status register. the status register data is la tched on the falling edge of the ch ip enable or output enable signals. either chip enable or output enable must be toggled to update the status register data. the read status register command can be issued at any time, even during program or erase operations. the read status register command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the status register. a read array command is required to return the bank to read array mode. see ta bl e 1 0 for the description of the status register bits.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 20/111 4.3 read electronic signature command the read electronic signature command reads the manufacturer and device codes, the lock status of the addressed bank, the protection register, and the configuration register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the protection register, or the configuration register (see ta b l e 9 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the parameter bank and the electronic signature location are not allowed (see table 16: dual operation limitations for details). if a read electronic signature command is issu ed to a bank that is executing a program or erase operation, the bank goes into read electronic signature mode. subsequent bus read cycles output the electronic signature data and the program/erase controller continue to program or erase in the background. the read electronic signature command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the electronic signature. a read array command is required to return the bank to read array mode. 4.4 read cfi query command the read cfi query command reads data from the common flash interface (cfi). one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank read from the common flash interface. the read cfi query command can be issued at any time, even during program or erase operations. if a read cfi query command is issued to a bank that is executing a program or erase operation the bank gos into read cfi query mode. subsequent bus read cycles output the cfi data and the program/erase controller continues to program or erase in the background. the read cfi query command only changes the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read from the cfi. a read array command is required to return the bank to read array mode. dual operations between the parameter bank and the cfi memory space are not allowed (see table 16: dual operation limitations for details). see appendix b: common flash interface and tables 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 and 51 for details on the information contained in the common flash interface memory area.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 21/111 4.5 clear status register command the clear status register command resets (set to ?0?) all error bits (sr1, 3, 4 and 5) in the status register. one bus write cycle is required to issue the clear status register command. the clear status register command does not affect the read mode of the bank. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command. 4.6 block erase command the block erase command erases a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation aborts, the data in the block does not change and the status register outputs the error. two bus write cycles are required to issue the command. the first bus cycle sets up the block erase command. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase confirm code, status register bits sr4 and sr5 are set and the command is aborted. once the command is issued the bank enters read status register mode and any read operation within the addressed bank outputs the contents of the status register. a read array command is required to return the bank to read array mode. during block erase operations the bank containing the block being erased only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands; all other commands are ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. refer to section 8: dual operations an d multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 18: program/erase times and endurance cycles . see appendix c , figure 22: block erase flowchart and pseudocode for a suggested flowchart for using the block erase command.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 22/111 4.7 blank check command the blank check command checks whether a main array block has been completely erased. only one block at a time can be checked. to use the blank check command v pp must be equal to v pph . if v pp is not equal to v pph , the device ignores the command and no error is shown in the status register. two bus cycles are required to issue the blank check command: the first bus cycle writes the blank check command (bch) to any address in the block to be checked. the second bus cycle writes the blank check confirm command (cbh) to any address in the block to be checked and starts the blank check operation. if the second bus cycle is not blank check confirm, status register bits sr4 and sr5 are set to '1' and the command aborts. once the command is issued, the addressed bank automatically enters the status register mode and further reads within the bank output the status register contents. the only operation permitted during blank check is read status register. dual operations are not supported while a blank check operation is in progress. blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. the sr7 status register bit indicates the status of the blank check operation in progress. sr7 = '0' means that the blank check operation is still ongoing, and sr7 = '1' means that the operation is complete. the sr5 status register bit goes high (sr5 = '1') to indicate that the blank check operation has failed. at the end of the operation the bank remains in the read status register mode until another command is written to the command interface. see appendix c , figure 19: blank check flowchart and pseudocode for a suggested flowchart for using the blank check command. typical blank check times are given in table 18: program/erase times and endurance cycles .
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 23/111 4.8 program command the program command programs a single word to the memory array. if the block being programmed is protected, then the program operation aborts, the data in the block does not change and the status register outputs the error. two bus write cycles are required to issue the program command: the first bus cycle sets up the program command. the second latches the address and data to be programmed and starts the program/erase controller. once the programming has started, read operations in the bank being programmed output the status register content. during a program operation, the bank containing the word being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands; all other commands are ignored. a read array command is required to return the bank to read array mode. refer to section 8: dual operations an d multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 18: program/erase times and endurance cycles . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. see appendix c , figure 18: program flowchart and pseudocode for the flowchart for using the program command. 4.9 buffer program command the buffer program command uses the device?s 32-word write buffer to speed up programming. up to 32 words can be loaded into the write buffer. the buffer program command dramatically reduces in-system programming time compared to the standard non- buffered program command. four successive steps are required to issue the buffer program command: 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. after the first bus write cycle, read operations in the bank output the contents of the status register. status register bit sr7 should be read to check that the buffer is available (sr7 = 1). if the buffer is not available (sr7 = 0), re-issue the buffer program command to update the status register contents. 2. the second bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 24/111 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. optimum performance is obtained when the start address corresponds to a 32 word boundary. 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program operation must lie within the same block. invalid address combinations or failing to follow the correct sequence of bus write cycles sets an error in the status register and aborts the operation without affecting the data in the memory array. if the status register bits sr4 and sr5 are set to '1', the buffer program command is not accepted. clear the status register before re-issuing the command. if the block being programmed is protected an error sets in the status register and the operation aborts without affecting the data in the memory array. during buffer program operations the bank being programmed only accepts the read array, read status register, read electronic signature, read cfi query and the program/erase suspend commands; all other commands are ignored. refer to section 8: dual operations an d multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. see appendix c , figure 20: buffer program flowchart and pseudocode for a suggested flowchart on using the buffer program command. 4.10 buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. if the block being programmed is protected, then the program operation aborts the data in the block does not change, and the status register outputs the error. the use of the buffer enhanced factory program command requires the following operating conditions: v pp must be set to v pph v dd must be within operating range ambient temperature t a must be 30c 10c the targeted block must be unlocked the start address must be aligned with the start of a 32 word buffer boundary the address must remain the start address throughout programming. dual operations are not supported during the buffer enhanced factory program operation and the command cannot be suspended.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 25/111 the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase, please refer to ta bl e 7 : fa c t o r y commands for detailed information. 4.10.1 setup phase the buffer enhanced factory program command requires two bus write cycles to initiate the command: the first bus write cycle sets up the buffer enhanced factory program command. the second bus write cycle confirms the command. after the confirm command is issued, read operations output the contents of the status register. the read status register command must not be issued or it is interpreted as data to program. the status register p/ec bit sr7 should be read to check that the p/ec is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program operation is terminated. see section 5: status register for details on the error. 4.10.2 program an d verify phase the program and verify phase requires 32 cycles to program the 32 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to program less than 32 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the command: 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/ec is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/ec increments the address location. if any address is given that is not in the same block as the start address, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/ec is ready for the next word. 3. once the write buffer is full, the data is programmed sequentially to the memory array. after the program operation the device automatically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to determine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 26/111 4.10.3 exit phase status register p/ec bit sr7 set to ?1? indicates that the device has exited the buffer enhanced factory program operation and returned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see section 5: status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. typical program times are given in ta bl e 1 8 . see appendix c , figure 26: buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the buffer enhanced factory program command. 4.11 program/erase suspend command the program/erase suspend command pauses a program or block erase operation. the command can be addressed to any bank. the program/erase resume command is required to restart the suspended operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register are set to ?1?. the following commands are accepted during program/erase suspend: ? program/erase resume ? read array (data from erase-suspended block or program-suspended word is not valid) ? read status register ? read electronic signature ? read cfi query ? clear status register additionally, if the suspended operation was a block erase then the following commands are also accepted: ? set configuration register ? program (except in erase-suspended block) ? buffer program (except in erase suspended blocks) ? block lock ? block lock-down ? block unlock. during an erase suspend the block being erased can be protected by issuing the block lock or block lock-down commands. when the program/erase resume command is issued the operation completes. it is possible to accumulate multiple suspend operations. for example,it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 27/111 if a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. the program/erase suspend command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode, the bank remains in that mode and outputs the corresponding data. refer to section 8: dual operations an d multiple bank architecture for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c , figure 21: program suspend and resume flowchart and pseudocode , and figure 23: erase suspend and resume flowchart and pseudocode for flowcharts for using the program/erase suspend command. 4.12 program/erase resume command the program/erase resume command restarts the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command. the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data. if a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. see appendix c , figure 21: program suspend and resume flowchart and pseudocode , and figure 23: erase suspend and resume flowchart and pseudocode for flowcharts for using the program/erase resume command. 4.13 protection register program command the protection register program command programs the user otp segments of the protection register and the two protection register locks. the device features 16 otp segments of 128 bits and one otp segment of 64 bits, as shown in figure 4: protection register memory map . the segments are programmed one word at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two bus write cycles are required to issue the protection register program command. the first bus cycle sets up the pr otection register program command. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the program operation has started. attempting to program a previously protected protection register results in a status register error.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 28/111 the protection register program cannot be suspended. dual operations between the parameter bank and the protection register memory space are not allowed (see ta bl e 1 6 : dual operation limitations for details) the two protection register locks protect the otp segments from further modification. the protection of the otp segments is not reversible. refer to figure 4: protection register memory map and table 9: protection register locks for details on the lock bits. see appendix c , figure 25: protection register program flowchart and pseudocode for a flowchart for using the protection register program command. 4.14 set configuration register command the set configuration register command writes a new value to the configuration register. two bus write cycles are required to issue the set configuration register comman: the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, that is a0 = cr0, a1 = cr1, ?, a15 = cr15. addresses a16-a22 are ignored. read operations output the array content after the set configuration register command is issued. the read electronic signature command is required to read the updated contents of the configuration register. 4.15 block lock command the block lock command locks a block and prevent program or erase operations from changing the data in it. all blocks are locked after power-up or reset. two bus write cycles are required to issue the block lock command: the first bus cycle sets up the block lock command. the second bus write cycle latches the block address and locks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 7 shows the lock status after issuing a block lock command. once set, the block lock bits remain set even after a hardware reset or power-down/power- up. they are cleared by a block unlock command. refer to section 9: block locking for a detailed explanation. see appendix c , figure 24: locking operations flowchart and pseudocode for a flowchart for using the lock command.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 29/111 4.16 block unlock command the block unlock command unlocks a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command: the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address and unlocks the block. the lock status can be monitored for each block using the read electronic signature command. ta b l e 1 7 shows the protection status after issuing a block unlock command. refer to section 9: block locking for a detailed explanation and appendix c , figure 24: locking operations flowchart and pseudocode for a flowchart for using the block unlock command. 4.17 block lock-down command the block lock-down command is used to lock down a locked or unlocked block. a locked-down block cannot be programmed or erased. the lock status of a locked-down block cannot be changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command: the first bus cycle sets up the block lock-down command. the second bus write cycle latches the block address and locks down the block. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. ta bl e 1 7 shows the lock status after issuing a block lock-down command. refer to section 9: block locking for a detailed explanation and appendix c , figure 24: locking operations flowchart and pseudocode for a flowchart for using the lock-down command.
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 30/111 table 6. standard commands (1) 1. x = don't care, wa = word address in targeted bank, rd =read data, srd =status register data, esd = electronic signature data, qd =query data, ba =block address, bka = bank address, pd = program data, pra = protection register address, pr d = protection register data, crd = configuration register data. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) 2. must be same bank as in the first cyc le. the signature addresses are listed in table 8 . srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write x 50h block erase 2 write bka or ba (3) 3. any address within the bank can be used. 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd buffer program (4) 4. n+1 is the number of words to be programmed. n+4 write ba e8h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 pd n+1 write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (3) 60h write ba 01h block unlock 2 write bka or ba (3) 60h write ba d0h block lock-down 2 write bka or ba (3) 60h write ba 2fh
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 31/111 table 7. factory commands command phase cycles bus write operations (1) 1. wa = word address in targeted bank, bka = bank addr ess, pd =program data, ba = block address, x = ?don?t care?. 1st 2nd 3rd final -1 final add data add data add data add data add data blank check 2 ba bch ba cbh buffer enhanced factory program setup 2 bka or wa (2) 2. any address within the bank can be used. 80h wa 1 d0h program/ verify (3) 3. the program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (4) 4. wa 1 is the start address, not ba 1 = not block address of wa 1 . x table 8. electronic signature codes code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 88c4 (m58lr128kt) 880d (m58lr256kt) bottom bank address + 01 88c5 (m58lr128kb) 880e (m58lr256kb) block protection locked block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 configuration register bank address + 05 cr (1) 1. cr = configuration register, prld = protection register lock data. protection register pr0 lock st factory default bank address + 80 0002 otp area permanently locked 0000 protection register pr0 bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 88 otp area protection register pr1 through pr16 lock bank address + 89 prld (1) protection registers pr1-pr16 bank address + 8a bank address + 109 otp area
command interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 32/111 figure 4. protection register memory map ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp protection register lock 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface 33/111 table 9. protection register locks lock description number address bits lock 1 80h bit 0 preprogrammed to protect unique device number, address 81h to 84h in pr0 bit 1 protects 64 bits of otp segment, address 85h to 88h in pr0 bits 2 to 15 reserved lock 2 89h bit 0 protects 128 bits of otp segment pr1 bit 1 protects 128 bits of otp segment pr2 bit 2 protects 128 bits of otp segment pr3 ---- ---- bit 13 protects 128 bits of otp segment pr14 bit 14 protects 128 bits of otp segment pr15 bit 15 protects 128 bits of otp segment pr16
status register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 34/111 5 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register (refer to section 4.2: read status register command for more details). to output the contents, the status regist er is latched and upd ated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank always read the status register during program and erase operations if no read array command has been issued. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. the bits in the status register are summarized in table 10: status register bits . refer to ta bl e 1 0 in conjunction with the following text descriptions. 5.1 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is high. 5.2 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase c ontroller inactive). sr6 is set within the erase suspend latency time of the program/erase suspend command being issued, therefore, the memory may still complete th e operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb status register 35/111 5.3 erase/blank check status bit (sr5) the erase/blank check status bit identifies if there was an error during a block erase operation. when the erase/blank check status bit is high (set to ?1?), the program/erase controller has applied th e maximum number of pulses to the block and still failed to verify that it has erased correctly. the erase/blank check status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). the erase/blank check status bit is also used to indicate whether an error occurred during the blank check operation. if the data at one or more locations in the block where the blank check command has been issued is different from ffffh, sr5 is set to '1'. once set high, the erase/blank check status bit must be set low by a clear status register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail. 5.4 program status bit (sr4) the program status bit identifies if there was an error during a program operation. it should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. attempting to program a '1' to an already programmed bit while v pp = v pph also sets the program status bit high. if v pp is different from v pph , sr4 remains low (set to '0') and the attempt is not shown. once set high, the program status bit must be set low by a clear status register command or a hardware reset before a new program command is issued, otherwise the new command appears to fail. 5.5 v pp status bit (sr3) the v pp status bit identifies an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an operation when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage. when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail.
status register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 36/111 5.6 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command being issued, therefor e, the memory may still comple te the operation rather than entering the suspend mode. when a program/erase resume command is issued the program suspend status bit returns low. 5.7 block protection status bit (sr1) the block protection status bit identifies if a program or block erase operation has tried to modify the contents of a locked or locked-down block. when the block protection status bit is high (set to ?1?), a program or erase operation has been attempted on a locked or locked-down block once set high, the block protection status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail. 5.8 bank write/multiple word program status bit (sr0) the bank write status bit indicates whether the addressed bank is programming or erasing. in buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. the bank write status bit should only be considered valid when the program/erase controller status bit sr7 is low (set to ?0?). when both the program/erase controller status bi t and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase controller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in buffer enhanced factory program mode if multiple word program status bit is low (set to ?0?), the device is ready for the next word. if the multiple word program status bit is high (set to ?1?) the device is not ready for the next word. for further details on how to use the status register, see the flowcharts and pseudocodes provided in appendix c .
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb status register 37/111 table 10. status register bits bit name type logic level (1) 1. logic level '1' is high, '0' is low. definition sr7 p/ec status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase/blank check status error '1' erase/blank check error '0' erase/blank check success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (buffer enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next buffer loading or is going to exit the befp mode '0' sr7 = ?1? the device has exited the befp mode sr7 = ?0? the device is ready for the next buffer loading
configuration register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 38/111 6 configuration register the configuration register configures the type of bus access that the memory performs. refer to section 7: read modes for details on read operations. the configuration register is set through the command interface using the set configuration register command. after a reset or power-up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in ta b l e 1 2 they specify the selection of the burst length, burst type, burst x latency and the read operation. refer to figures 5 and 6 for examples of synchronous burst configurations. 6.1 read select bit (cr15) the read select bit, cr15, switches between asynchronous and synchronous read operations. when the read select bit is set to ?1?, read operations are asynchronous, and when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access. 6.2 x latency bits (cr13-cr11) the x latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. refer to figure 5: x latency and data output configuration example . for correct operation the x latency bits can only assume the values in table 12: configuration register . ta bl e 1 1 shows how to set the x latency parameter, taking into account the speed class of the device and the frequency used to read the flash memory in synchronous mode. table 11. x latency settings fmax t k min x latency min 30 mhz 33 ns 3 40 mhz 25 ns 4 54 mhz 19 ns 5 66 mhz 15 ns 5
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb configuration register 39/111 6.3 wait polarity bit (cr10) the wait polarity bit is used to set the polarity of the wait signal used in synchronous burst read mode. during synchronous burst read mode the wait signal indicates whether the data output are valid or a wait state must be inserted. when the wait polarity bit is set to ?0? the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high. 6.4 data output configuration bit (cr9) the data output configuration bit configures the output to remain valid for either one or two clock cycles during synchronous mode. when the data output configuration bit is ?0? the output data is valid for one clock cycle, and when the data output configuration bit is ?1? the output data is valid for two clock cycles. the data output configuration bit must be configured using the following condition: t k > t kqv + t qvk_cpu where t k is the clock period t qvk_cpu is the data setup time required by the system cpu t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cycles). refer to figure 5: x latency and data output configuration example . 6.5 wait configuration bit (cr8) the wait configuration bit is used to control the timing of the wait output pin, wait, in synchronous burst read mode. when wait is asserted, data is not valid and when wait is de-asserted, data is valid. when the wait configuration bit is low (set to ?0?) the wait output pin is asserted during the wait state. when the wait configuration bit is high (set to ?1?), the wait output pin is asserted one data cycle before the wait state. 6.6 burst type bit (cr7) the burst type bit determines the sequence of addresses read during synchronous burst reads. the burst type bit is high (set to ?1?), as the memory outputs from sequential addresses only. see table 13: burst type definition for the sequence of addresses output from a given starting address in sequential mode.
configuration register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 40/111 6.7 valid clock edge bit (cr6) the valid clock edge bit, cr6, configures the active edge of the clock, k, during synchronous read operations. wh en the valid clock edge bit is low (set to ?0?) the falling edge of the clock is the active edge. when the valid clock edge bit is high (set to ?1?) the rising edge of the clock is the active edge. 6.8 wrap burst bit (cr3) the wrap burst bit, cr3, selects between wrap and no wrap. synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is low (set to ?0?) the burst read wraps. when it is high (set to ?1?) the burst read does not wrap. 6.9 burst length bits (cr2-cr0) the burst length bits sets the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the wait signal to indicate that a delay is necessary before the data is output. if the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, wait is asserted for 1, 2 or 3 clock cycles, respectively. when the burst sequence crosses the first 16-word boundary this indicates that the device needs an internal delay to read the successive words in the array. waitis asserted only once during a continuous burst access. see also table 13: burst type definition . cr14, cr5 and cr4 are reserved for future use.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb configuration register 41/111 table 12. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x latency 010 2 clock latency (1) 1. the combination x latency=2, data held for two cloc k cycles and wait active one data cycle before the wait state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) other configurations reserved cr10 wait polarity 0 wait is active low 1 wait is active high (default) cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) (1) cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (1) (default) cr7 burst type 0reserved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 011 16 words 111 continuous (default)
configuration register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 42/111 table 13. burst type definition mode start addr sequential continuous burst 4 words 8 words 16 words wrap 0 0-1-2-3 0-1-2-3-4-5-6- 7 0-1-2-3-4-5-6-7-8-9-10- 11-12-13-14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7- 0 1-2-3-4-5-6-7-8-9-10- 11-12-13-14-15-0 1-2-3-4-5-6-7-...15-wait-16-17- 18... 2 2-3-0-1 2-3-4-5-6-7-0- 1 2-3-4-5-6-7-8-9-10-11- 12-13-14-15-0-1 2-3-4-5-6-7...15-wait-wait-16- 17-18... 3 3-0-1-2 3-4-5-6-7-0-1- 2 3-4-5-6-7-8-9-10-11-12- 13-14-15-0-1-2 3-4-5-6-7...15-wait-wait- wait-16-17-18... ... 7 7-4-5-6 7-0-1-2-3-4-5- 6 7-8-9-10-11-12-13-14- 15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-wait- wait-wait-16-17... ... 12 12-13-14-15-16-17-18... 13 13-14-15-wait-16-17-18... 14 14-15-wait-wait-16-17-18.... 15 15-wait-wait-wait-16-17-18...
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb configuration register 43/111 no-wrap 0 0-1-2-3 0-1-2-3-4-5-6- 7 0-1-2-3-4-5-6-7-8-9-10- 11-12-13-14-15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7- 8 1-2-3-4-5-6-7-8-9-10- 11-12-13-14-15-wait- 16 2 2-3-4-5 2-3-4-5-6-7-8- 9... 2-3-4-5-6-7-8-9-10-11- 12-13-14-15-wait- wait-16-17 3 3-4-5-6 3-4-5-6-7-8-9- 10 3-4-5-6-7-8-9-10-11-12- 13-14-15-wait-wait- wait-16-17-18 ... 7 7-8-9-10 7-8-9-10-11- 12-13-14 7-8-9-10-11-12-13-14- 15-wait-wait-wait- 16-17-18-19-20-21-22 ... 12 12-13-14- 15 12-13-14-15- 16-17-18-19 12-13-14-15-16-17-18- 19-20-21-22-23-24-25- 26-27 13 13-14-15- wait-16 13-14-15- wait-16-17- 18-19-20 13-14-15-wait-16-17- 18-19-20-21-22-23-24- 25-26-27-28 14 14-15- wait- wait-16- 17 14-15-wait- wait-16-17- 18-19-20-21 14-15-wait-wait-16- 17-18-19-20-21-22-23- 24-25-26-27-28-29 15 15-wait- wait- wait-16- 17-18 15-wait- wait-wait- 16-17-18-19- 20-21-22 15-wait-wait-wait- 16-17-18-19-20-21-22- 23-24-25-26-27-28-29- 30 table 13. burst type definition (continued) mode start addr sequential continuous burst 4 words 8 words 16 words
configuration register m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 44/111 figure 5. x latency and data output configuration example 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. 2. the settings shown are x latency = 4, data output held for one clock cycle. ai14014 amax-a0 (1) valid address k l dq15-dq0 valid data x-latency valid data tk tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle e
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb configuration register 45/111 figure 6. wait configuration example 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. ai14015 amax-a0 (1) valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
read modes m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 46/111 7 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see section 6: configuration register for details). all banks support both asynchronous and synchronous read operations. 7.1 asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, that is the memory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. asynchronous read operations can be performed in two different ways, asynchronous random access read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. in asynchronous read mode a page of data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by address inputs a0 and a1. the first read operation within the page has a longer access time (t avqv , random access time), subsequent reads within the same page have much shorter access times (t avqv1 , page access time). if the page changes then the normal, longer timings apply again. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always deasserted. see table 24: asynchronous read ac characteristics , figure 9: asynchronous random access read ac waveforms and figure 10: asynchronous page read ac waveforms for details.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb read modes 47/111 7.2 synchronous burst read mode in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode c an only be used to read the memory array. for other read operations, such as read status register, read cfi , and read electronic signature, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence starts at the first clock ed ge (rising or falling dep ending on valid clock edge bit cr6 in the configurat ion register) after the falling ed ge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr13-cr11 of the configuration register. the number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output configuration bit cr9). the order of the data output can be modified through the wrap burst bit in the configuration register. the burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). the wait signal may be asserted to indicate to the system that an ou tput delay will occur. this delay depends on the starting addres s of the burst sequence and on the burst configuration. wait is asserted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only de-asserted when output data are valid. in continuous burst read mode a wait state occurs when crossing the first 16 word boundary. if the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 25: synchronous read ac characteristics and figure 11: synchronous burst read ac waveforms for details.
read modes m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 48/111 7.2.1 synchronous burst read suspend a synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. it can be suspended during the initial access latency time (before data is output) or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspended when chip enable, e , is low and the current address has been latched (on a latch enable rising edge or on a valid clock edge). the clock signal is then halted at v ih or at v il , and output enable, g , goes high. when output enable, g , becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. wait reverts to high-impedance when chip enable, e , or output enable, g , goes high. see table 25: synchronous read ac characteristics and figure 13: synchronous burst read suspend ac waveforms for details. 7.3 single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or the protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is asserted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only de-asserted when output data are valid. see table 25: synchronous read ac characteristics and figure 12: single synchronous read ac waveforms for details.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dual operations and multiple bank ar- 49/111 8 dual operations and multiple bank architecture the multiple bank architectu re of the m58lrxxxkt/b gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. in addition, if the suspended operation is erase then a program command can be issued to another block. this means the device can have one block in erase suspend mode, one programming, and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, read operations are possible at any moment in the m58lrxxxkt/b device. dual operations between the parameter bank and either of the cfi, the otp or the electronic signature memory space are not allowed. ta b l e 1 6 shows which dual operations are allowed or not between the cfi, the otp, the electronic signature locations and the memory array. ta bl e s 14 and 15 show the dual operations possible in other banks and in the same bank. table 14. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program, buffer program block erase program /erase suspend program /erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended ye s ye s ye s ye s ? ? ? ye s erase suspended ye s ye s ye s ye s ye s ? ? ye s
dual operations and multiple bank architecture m58lr128kt, m58lr128kb, m58lr256kt, 50/111 table 15. dual operations allowed in same bank status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program, buffer program block erase program /erase suspend program /erase resume i d l e ye s ye s ye s ye s ye s ye s ye s ye s programming ? (1) 1. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. ye s ye s ye s ? ? ye s ? erasing ? (1) ye s ye s ye s ? ? ye s ? program suspended ye s (2) 2. not allowed in the block that is being erased or in the word that is being programmed. ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s (1) ?? yes table 16. dual operation limitations current status commands allowed read cfi / otp / electronic signature read parameter blocks read main blocks located in parameter bank not located in parameter bank programming/erasing parameter blocks no no no yes programming/ erasing main blocks located in parameter bank ye s n o n o ye s not located in parameter bank ye s ye s ye s in different bank only programming otp no no no no
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb block locking 51/111 9 block locking the m58lrxxxkt/b features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. this locking scheme has three levels of protection. lock/unlock - this first level allows so ftware only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and locked-down. ta bl e 1 7 , defines all of the possible protection states (wp , dq1, dq0), and appendix c , figure 24 shows a flowchart for the locking operations. 9.1 reading block lock status the lock status of every block can be read in read electronic signature mode of the device. to enter this mode issue the read electronic signature command. subsequent reads at the address specified in ta bl e 8 output the protection status of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. dq0 is automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock- down command. dq1 cannot be cleared by software, except a hardware reset or power- down. the following sections explain the operation of the locking system. 9.2 locked state the default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from program or erase operations. any program or erase operations attempted on a lo cked block will return an error in the status register. the status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. 9.3 unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by issuing the unlock command.
block locking m58lr128kt, m58lr1 28kb, m58lr256kt, m58lr256kb 52/111 9.4 lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked down by issuing the lock-down command. locked-down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the write protect, wp , input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. when the lock-down function is disabled (wp =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. when wp =0 blocks that were previously locked-down return to the lock- down state (0,1,x) regardless of any changes that were made while wp =1. device reset or power-down resets all blocks, including those in lock-down, to the locked state. 9.5 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status is changed. after completing any desired lock, read, or program operations, resume the erase operation with the erase resume command. if a block is locked or locked down during an erase suspend of the same block, the locking status bits is changed immediately, but when the erase is resumed, the erase operation completes. locking operations cannot be performed during a program suspend.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb block locking 53/111 table 17. lock status current protection status (1) (wp , dq1, dq0) 1. the lock status is defined by the write protect pin and by dq1 (?1? for a locked-dow n block) and dq0 (?1? for a locked block) as read in the read elec tronic signature command with dq1 = v ih and dq0 = v il . next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) 2. all blocks are locked at power-up, so the de fault configuration is 001 or 101 according to wp status. no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) 3. a wp transition to v ih on a locked block will restore the pr evious dq0 value, giving a 111 or 110.
program and erase times and endurance cycles m58lr128kt, m58lr128kb, m58lr256kt, 54/111 10 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 8 . exact erase times may change depending on the memory array condition. the best case is when all the bits in the block are at ?0? (pre-programmed). the worst case is when all the bits in the block are at ?1? (not preprogrammed). usually, the system overhead is negligible with respect to the erase time. in the m58lrxxxkt/b the maximum number of program/erase cycles depends on the v pp voltage supply used. table 18. program/erase times and endurance cycles (1) (2) parameter condition min typ typical after 100kw/e cycles max unit v pp = v dd erase parameter block (16 kword) 0.4 1 2.5 s main block (64 kword) preprogrammed 1.2 3 4 s not preprogrammed 1.5 4 s program (3) single word word program 12 180 s buffer program 12 180 s buffer (32 words) (buffer program) 384 s main block (64 kword) 768 ms suspend latency program 20 25 s erase 20 25 s program/erase cycles (per block) main blocks 100 000 cycles parameter blocks 100 000 cycles
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb program and erase times and endur- 55/111 v pp = v pph erase parameter block (16 kword) 0.4 2.5 s main block (64 kword) 1 4 s program (3) single word word program 10 170 s buffer enhanced factory program (4) 2.5 s buffer (32 words) buffer program 80 s buffer enhanced factory program 80 s main block (64 kwords) buffer program 160 ms buffer enhanced factory program 160 ms bank (8 mbits) buffer program 1.28 s buffer enhanced factory program 1.28 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles blank check main blocks 16 ms parameter blocks 4 ms 1. t a = ?25 to 85 c; v dd = 1.7 v to 2 v; v ddq = 1.7 v to 2 v. 2. values are liable to change with t he external system-level overhead (command sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. this is an average value on the entire device. table 18. program/erase times and endurance cycles (1) (2) (continued) parameter condition min typ typical after 100kw/e cycles max unit
maximum ratings m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 56/111 11 maximum ratings stressing the device above the rating listed in the table 19: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliabilit y. refer also to the numonyx sure program and other relevant quality documents. table 19. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?65 125 c v io input or output voltage ?0.5 v ddq + 0.6 v v dd supply voltage ?0.2 2.5 v v ddq input/output supply voltage ?0.2 2.5 v v pp program voltage ?0.2 10 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 57/111 12 dc and ac parameters this section summarizes the operating measurement conditions and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables in this section are derived from tests performed under the measurement conditions summarized in table 20: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 7. ac measurement i/o waveform table 20. operating and ac measurement conditions parameter m58lrxxxkt/b unit 70 ns 85 ns min max min max v dd supply voltage 1.7 2.0 1.7 2.0 v v ddq supply voltage 1.7 2.0 1.7 2.0 v v pp supply voltage (factory environment) 8.5 9.5 8.5 9.5 v v pp supply voltage (application environment) ?0.4 v ddq +0.4 ?0.4 v ddq +0.4 v ambient operating temperature ?25 85 ?25 85 c load capacitance (c l )3030pf input rise and fall times 5 5 ns input pulse voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai06161 v ddq 0v v ddq /2
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 58/111 figure 8. ac measurement load circuit table 21. capacitance (1) 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0 v 6 8 pf c out output capacitance v out = 0 v 8 12 pf ai06162 v ddq c l c l includes jig capacitance 16.7k device under test 0.1f v dd 0.1f v ddq 16.7k
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 59/111 table 22. dc characteristics - currents symbol parameter test condition typ max unit i li input leakage current 0 v v in v ddq 1 a i lo output leakage current 0 v v out v ddq 1 a i dd1 supply current asynchronous read (f = 5 mhz) e = v il , g = v ih 13 15 ma supply current synchronous read (f = 54 mhz) 4 word 18 20 ma 8 word 20 22 ma 16 word 25 27 ma continuous 28 30 ma supply current synchronous read (f = 66 mhz) 4 word 20 22 ma 8 word 22 24 ma 16 word 27 29 ma continuous 30 32 ma i dd2 supply current (reset) 128 mbit rp = v ss 0.2 v 22 70 a 256 mbit 70 110 i dd3 supply current (standby) 128 mbit e = v dd 0.2 v k=v ss 22 70 a 256 mbit 70 110 i dd4 supply current (automatic standby) e = v il , g = v ih 22 50 a i dd5 (1) supply current (program) v pp = v pph 10 30 ma v pp = v dd 20 35 ma supply current (erase) v pp = v pph 10 30 ma v pp = v dd 20 35 ma i dd6 (1),(2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 33 50 ma program/erase in one bank, synchronous read (continuous f = 66 mhz) in another bank 50 67 ma i dd7 (1) supply current program/erase suspended (standby) 128 mbit e = v dd 0.2 v k=v ss 22 70 a 256 mbit 70 110 i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 60/111 i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. table 22. dc characteristics - currents symbol parameter test condition typ max unit table 23. dc characteristics - voltages symbol parameter test co ndition min typ max unit v il input low voltage 0 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage i oh = ?100 a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.3 1.8 3.3 v v pph v pp program voltage factory program, erase 8.5 9.0 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1v
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 61/111 figure 9. asynchronous random access read ac waveforms ai14016 tavav telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-amax(1) valid valid l (2) tellh tllqv tlllh tavlh tlhax taxqx wait (3) teltv tehtz hi-z hi-z tavqv tgltv tghtz notes: 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. 2. latch enable, l, can be kept low (also at board level) when the latch enable function is not required or supporte d. 3. write enable, w, is high, wait is active low.
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 62/111 figure 10. asynchronous page read ac waveforms ai14017 a2-amax (1) e g a0-a1 valid address l dq0-dq15 valid address valid address valid address valid address valid data valid data valid data valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv (2) notes: 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. 2. wait is active low. valid address latch outputs enabled valid data standby tlhgl hi-z
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 63/111 table 24. asynchronous read ac characteristics symbol alt parameter m58lrxxxkt/b unit 70 85 read timings t avav t rc address valid to next address valid min 70 85 ns t avqv t acc address valid to output valid (random) max 70 85 ns t avqv1 t pag e address valid to output valid (page) max 20 25 ns t axqx (1) 1. sampled only, not 100% tested. t oh address transition to output transition min 0 0 ns t eltv chip enable low to wait valid max 11 14 ns t elqv (2) 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . t ce chip enable low to output valid max 70 85 ns t elqx (1) t lz chip enable low to output transition min 0 0 ns t ehtz chip enable high to wait hi-z max 11 14 ns t ehqx (1) t oh chip enable high to output transition min 2 2 ns t ehqz (1) t hz chip enable high to output hi-z max 14 14 ns t glqv (2) t oe output enable low to output valid max 20 20 ns t glqx (1) t olz output enable low to output transition min 0 0 ns t gltv output enable low to wait valid max 14 14 ns t ghqx (1) t oh output enable high to output transition min 2 2 ns t ghqz (1) t df output enable high to output hi-z max 14 14 ns t ghtz output enable high to wait hi-z max 14 14 ns latch timings t avlh t avadvh address valid to latch enable high min 7 7 ns t ellh t eladvh chip enable low to latch enable high min 10 10 ns t lhax t advhax latch enable high to address transition min 7 7 ns t lllh t advladvh latch enable pulse width min 7 7 ns t llqv t advlqv latch enable low to output valid (random) max 70 85 ns
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 64/111 figure 11. synchronous burst read ac waveforms ai14018 dq0-dq15 e g a0-amax (5) l wait k (4) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tehqx tehqz tghqx tghqz hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the activ e edge of k is the rising one. 5. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. tehel hi-z tgltv
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 65/111 figure 12. single synchronous read ac waveforms 1. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. 2. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the active edge is the rising one. 3. the wait signal is configured to be active dur ing wait state. wait signal is active low. ai14019 e g a0-amax (1) l wait (3) k (2) valid address tglqv tavkh tllkh telkh hi-z telqx tkhqv tglqx tkhtv dq0-dq15 valid hi-z telqv tgltv tghtz
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 66/111 figure 13. synchronous burst read suspend ac waveforms ai14020 dq0-dq15 e g a0-amax (5) l wait (2) k (4) valid valid valid address tlllh tavlh tavkh tllkh telkh tkhax valid valid note 1 tehqx tehqz tghqx hi-z teltv tkhqv tehtz notes 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock sign al, k, can be configured as the active edge. here, the active edge is the rising one. 5. amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b. tglqx tehel tghqz tglqv note 3 hi-z tgltv tghtz
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 67/111 figure 14. clock input ac waveform table 25. synchronous read ac characteristics (1) (2) 1. sampled only, not 100% tested. 2. for other timings please refer to table 24: asynchronous r ead ac characteristics . symbol alt parameter m58lrxxxkt/b unit 70 85 synchronous read timings t avkh t avclkh address valid to clock high min 7 7 ns t elkh t elclkh chip enable low to clock high min 7 7 ns t eltv chip enable low to wait valid max 14 14 ns t ehel chip enable pulse width (subsequent synchronous reads) min 14 14 ns t ehtz chip enable high to wait hi-z max 14 14 ns t khax t clkhax clock high to address transition min 7 7 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 11 14 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 3 3 ns t llkh t advlclkh latch enable low to clock high min 7 7 ns clock specifications t khkh t clk clock period (f = 54 mhz) min 18.5 ns clock period (f = 66 mhz) 15 ns t khkl t klkh clock high to clock low clock low to clock high min 4.5 4.5 ns t f t r clock fall or rise time max 3 3 ns ai06981 tkhkh tf tr tkhkl tklkh
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 68/111 figure 15. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-amax (1) tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai14021 twphwh wp twhgl tqvwpl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhwpl twhvpl telkv k twhll twhav note: amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 69/111 table 26. write ac characteristics, write enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter m58lrxxxkt/b unit 70 85 write enable controlled timings t avav t wc address valid to next address valid min 70 85 ns t avlh address valid to latch enable high min 7 7 ns t avwh (2) address valid to write enable high min 45 45 ns t dvwh t ds data valid to write enable high min 45 45 ns t ellh chip enable low to latch enable high min 10 10 ns t elwl t cs chip enable low to write enable low min 0 0 ns t elqv chip enable low to output valid min 70 85 ns t elkv chip enable low to clock valid min 7 7 ns t ghwl output enable high to write enable low min 17 17 ns t lhax latch enable high to address transition min 7 7 ns t lllh latch enable pulse width min 7 7 ns t whav (2) 2. meaningful only if l is always kept low. write enable high to address valid min 0 0 ns t whax (2) t ah write enable high to address transition min 0 0 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whel (3) 3. t whel and t whll have this value when reading in the tar geted bank or when reading following a set configuration register command. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a set confi guration register command. if the first read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel and t whll is 0 ns. write enable high to chip enable low min 25 25 ns t whgl write enable high to output enable low min 0 0 ns t whll (3) write enable high to latch enable low min 25 25 ns t whwl t wph write enable high to write enable low min 25 25 ns t wlwh t wp write enable low to write enable high min 45 45 ns protection timings t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vphwh t vps v pp high to write enable high min 200 200 ns t whvpl write enable high to v pp low min 200 200 ns t whwpl write enable high to write protect low min 200 200 ns t wphwh write protect high to write enable high min 200 200 ns
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 70/111 figure 16. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-amax (1) tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai14022 twpheh wp tehgl tqvwpl twhel bank address valid address l tavlh tlllh tlhax tghel tehwpl tehvpl telkv k tellh note: amax is equal to a22 in the m58lr128kt/b and, to a23 in the m58lr256kt/b.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb dc and ac parameters 71/111 table 27. write ac characteristics, chip enable controlled (1) 1. sampled only, not 100% tested. symbol alt parameter m58lrxxxkt/b unit 70 85 chip enable controlled timings t avav t wc address valid to next address valid min 70 85 ns t aveh address valid to chip enable high min 45 45 ns t avlh address valid to latch enable high min 7 7 ns t dveh t ds data valid to chip enable high min 45 45 ns t ehax t ah chip enable high to address transition min 0 0 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehel t cph chip enable high to chip enable low min 25 25 ns t ehgl chip enable high to output enable low min 0 0 ns t ehwh t ch chip enable high to write enable high min 0 0 ns t elkv chip enable low to clock valid min 7 7 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t ellh chip enable low to latch enable high min 10 10 ns t elqv chip enable low to output valid min 70 85 ns t ghel output enable high to chip enable low min 17 17 ns t lhax latch enable high to address transition min 7 7 ns t lllh latch enable pulse width min 7 7 ns t whel (2) 2. t whel has this value when reading in the targeted bank or when reading following a set configuration register command. system designer s should take this into account and may insert a software no-op instruction to delay the first read in the same bank a fter issuing any command and to delay the first read to any address after issuing a set conf iguration register command. if the first read after the command is a read array operation in a different bank and no changes to the configuration register have been issued, t whel is 0ns. write enable high to chip enable low min 25 25 ns t wlel t cs write enable low to chip enable low min 0 0 ns protection timings t ehvpl chip enable high to v pp low min 200 200 ns t ehwpl chip enable high to write protect low min 200 200 ns t qvvpl output (status register) valid to v pp low min 0 0 ns t qvwpl output (status register) valid to write protect low min 0 0 ns t vpheh t vps v pp high to chip enable high min 200 200 ns t wpheh write protect high to chip enable high min 200 200 ns
dc and ac parameters m58lr128kt, m5 8lr128kb, m58lr256kt, m58lr256kb 72/111 figure 17. reset and power-up ac waveforms ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll table 28. reset and power-up ac characteristics symbol parameter test condition m58lrxxxkt/b unit t plwl t plel t plgl t plll reset low to write enable low reset low to chip enable low, reset low to output enable low, reset low to latch enable low during program min 25 s during erase min 25 s other conditions min 80 ns t phwl t phel t phgl t phll reset high to write enable low reset high to chip enable low reset high to output enable low reset high to latch enable low min 30 ns t plph (1),(2) rp pulse width min 50 ns t vdhph (3) supply voltages high to reset high min 300 s 1. the device reset is possible but not guaranteed if t plph < 50 ns. 2. sampled only, not 100% tested. 3. it is important to assert rp to allow proper cpu initiali zation during power-up or reset.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb part numbering 73/111 13 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the numonyx sales office nearest to you. table 29. ordering information scheme example: m58lr128kt 70 5 device type m58 architecture l = multilevel, multiple bank, burst mode operating voltage r = v dd = 1.7 v to 2.0 v, v ddq = 1.7 v to 2.0 v density 128 = 128 mbit (x16) 256 = 256 mbit (x16) technology k = 65 nm technology parameter location t = top boot b = bottom boot speed 70 = 70 ns 85 = 85 ns package not packaged separately (1) 1. the m58lrxxxkt/b are only availabl e as part of a multichip package. temperature range 5 = ?25 to 85 c
block address tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 74/111 appendix a block address tables the following set of equations can be used to calculate a complete set of block addresses for the m58lrxxxkt/b using the information contained in tables 33 to 41 . to calculate the block base address from the block number: first it is necessary to calculate the bank number and the block number offset. this can be achieved using the following formulas: bank_number = (block_number ? 3) / 8 block_number_offset = block_number ? 3 ? (bank_number x 8), if bank_number= 0, the block base address can be directly read from tables 33 and 39 (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. otherwise: block_base_address = bank_base_address + block_base_address_offset to calculate the bank number and the block number from the block base address: if the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from tables 33 and 39 (parameter bank block addresses), in the block number column, in the row that corresponds to the address given. otherwise, the block number can be calculated using the formulas below: for the top configuration (m58lr256kt and m58lr128kt): block_number = ((not address) / 2 16 ) + 3 for the bottom configuration (m58lr256kb and m58lr128kb): block_number = (address / 2 16 ) + 3 for both configurations the bank number and the block number offset can be calculated using the following formulas: bank_number = (block_number ? 3) / 8 block_number_offset = block_number ? 3 ? (bank_number x 8)
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb block address tables 75/111 table 30. m58lr128kt - parameter bank block addresses block number size (kwords) address range 0 16 7fc000-7fffff 1 16 7f8000-7fbfff 2 16 7f4000-7f7fff 3 16 7f0000-7f3fff 4 64 7e0000-7effff 5 64 7d0000-7dffff 6 64 7c0000-7cffff 7 64 7b0000-7bffff 8 64 7a0000-7affff 9 64 790000-79ffff 10 64 780000-78ffff table 31. m58lr128kt - main bank base addresses bank number (1) 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 1 11-18 70 0000 2 19-26 68 0000 3 27-34 60 0000 4 35-42 58 0000 5 43-50 50 0000 6 51-58 48 0000 7 59-66 40 0000 8 67-74 38 0000 9 75-82 30 0000 10 83-90 28 0000 11 91-98 20 0000 12 99-106 18 0000 13 107-114 10 0000 14 115-122 08 0000 15 123-130 00 0000
block address tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 76/111 table 32. m58lr128kt - block addresses in main banks block number offset block base address offset 0 07 0000 1 06 0000 2 05 0000 3 04 0000 4 03 0000 5 02 0000 6 01 0000 7 00 0000 table 33. m58lr256kt - parameter bank block addresses block number size (kwords) address range 0 16 ffc000-ffffff 1 16 ff8000-ffbfff 2 16 ff4000-ff7fff 3 16 ff0000-ff3fff 4 64 fe0000-feffff 5 64 fd0000-fdffff 6 64 fc0000-fcffff 7 64 fb0000-fbffff 8 64 fa0000-faffff 9 64 f90000-f9ffff 10 64 f80000-f8ffff 11 64 f70000-f7ffff 12 64 f60000-f6ffff 13 64 f50000-f5ffff 14 64 f40000-f4ffff 15 64 f30000-f3ffff 16 64 f20000-f2ffff 17 64 f10000-f1ffff 18 64 f00000-f0ffff
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb block address tables 77/111 table 34. m58lr256kt - main bank base addresses bank number (1) 1. there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 1 19-34 e00000 2 35-50 d00000 3 51-66 c00000 4 67-82 b00000 5 83-98 a00000 6 99-114 900000 7 115-130 800000 8 131-146 700000 9 147-162 600000 10 163-178 500000 11 179-194 400000 12 195-210 300000 13 211-226 200000 14 227-242 100000 15 243-258 000000 table 35. m58lr256kt - block addresses in main banks block number offset block base address offset 0 0f0000 1 0e0000 2 0d0000 3 0c0000 4 0b0000 5 0a0000 6 090000 7 080000 8 070000 9 060000 10 050000 11 040000 12 030000 13 020000 14 010000 15 000000
block address tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 78/111 table 36. m58lr128kb - parameter bank block addresses block number size (kwords) address range 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff table 37. m58lr128kb - main bank base addresses bank number (1) 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). block numbers bank base address 15 123-130 78 0000 14 115-122 70 0000 13 107-114 68 0000 12 99-106 60 0000 11 91-98 58 0000 10 83-90 50 0000 9 75-82 48 0000 8 67-74 40 0000 7 59-66 38 0000 6 51-58 30 0000 5 43-50 28 0000 4 35-42 20 0000 3 27-34 18 0000 2 19-26 10 0000 1 11-18 08 0000
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb block address tables 79/111 table 38. m58lr128kb - block addresses in main banks block number offset block base address offset 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000 table 39. m58lr256kb - parameter bank block addresses block number size (kwords) address range 18 64 0f0000-0fffff 17 64 0e0000-0effff 16 64 0d0000-0dffff 15 64 0c0000-0cffff 14 64 0b0000-0bffff 13 64 0a0000-0affff 12 64 090000-09ffff 11 64 080000-08ffff 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
block address tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 80/111 1. there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 40. m58lr256kb - main bank base addresses bank number block numbers bank base address 15 243-258 f00000 14 227-242 e00000 13 211-226 d00000 12 195-210 c00000 11 179-194 b00000 10 163-178 a00000 9 147-162 900000 8 131-146 800000 7 115-130 700000 6 99-114 600000 5 83-98 500000 4 67-82 400000 3 51-66 300000 2 35-50 200000 1 19-34 100000 table 41. m58lr256kb - block addresses in main banks block number offset block base address offset 15 0f0000 14 0e0000 13 0d0000 12 0c0000 11 0b0000 10 0a0000 9 090000 8 080000 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb common flash interface 81/111 appendix b common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 and 51 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is written (see figure 4: protection register memory map ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by numonyx. issue a read array command to return to read mode. 1. the flash memory display the cfi data structure w hen cfi query command is issued. in this table are listed the main sub-sections detailed in tables 43 , 44 , 45 and 46 . query data is always presented on the lowest order data outputs. table 42. query structure overview offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string command set id and algorithm data offset 01bh system interface information dev ice timing and voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp
common flash interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 82/111 table 43. cfi query identification string offset sub-section name description value 000h 0020h manufacturer code st 001h 88c4h 88c5h 880dh 880eh device code m58lr128kt m58lr128kb m58lr256kt m58lr256kb to p bottom to p bottom 002h-00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0001h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 014h 0000h 015h offset = p = 000ah address for primary algorithm extended query table (see ta b l e 4 6 ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb common flash interface 83/111 table 44. cfi query system interface information offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5v 01fh 0004h typical time-out per single byte/word program = 2 n s 16s 020h 0009h typical time-out for buffer program = 2 n s 512s 021h 000ah typical time-out per individual block erase = 2 n ms 1s 022h 0000h typical time-out for full chip erase = 2 n ms na 023h 0004h maximum time-out for word program = 2 n times typical 256s 024h 0004h maximum time-out for buffer program = 2 n times typical 8192s 025h 0002h maximum time-out per individual block erase = 2 n times typical 4s 026h 0000h maximum time-out for chip erase = 2 n times typical na
common flash interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 84/111 table 45. device geometry definition offset data description value 027h 0018h m58lr128kt/b device size = 2 n in number of bytes 16 mbytes 0019h m58lr256kt/b device size = 2 n in number of bytes 32 mbytes 028h 029h 0001h 0000h flash device interface code description x16 async. 02ah 02bh 0006h 0000h maximum number of bytes in multi-byte program or page = 2 n 64 bytes 02ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 top devices 02dh 02eh 007eh 0000h m58lr128kt/b erase block region 1 information number of identical-size erase blocks = 007eh+1 127 00feh 0000h m58lr256kt/b erase block region 1 information number of identical-size erase blocks = 00feh+1 255 02fh 030h 0000h 0002h erase block region 1 information block size in region 1 = 0200h * 256 byte 128 kbyte 031h 032h 0003h 0000h erase block region 2 information number of identical-size erase blocks = 0003h+1 4 033h 034h 0080h 0000h erase block region 2 information block size in region 2 = 0080h * 256 byte 32 kbyte 035h 038h reserved reserved for future erase block region information na bottom devices 02dh 02eh 0003h 0000h erase block region 1 information number of identical-size erase block = 0003h+1 4 02fh 030h 0080h 0000h erase block region 1 information block size in region 1 = 0080h * 256 bytes 32 kbytes 031h 032h 007eh 0000h m58lr128kt/b erase block region 2 information number of identical-size erase block = 007eh+1 127 00feh 0000h m58lr256kt/b erase block region 2 information number of identical-size erase block = 00feh+1 255 033h 034h 0000h 0002h erase block region 2 information block size in region 2 = 0200h * 256 bytes 128 kbytes 035h 038h reserved reserved for future erase block region information na
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb common flash interface 85/111 table 46. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h =10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0033h minor version number, ascii "3" (p+5)h = 10fh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported(1 = yes, 0 = no) bit 1 erase suspend supported(1 = yes, 0 = no) bit 2 program suspend supported(1 = yes, 0 = no) bit 3 legacy lock/unlock supported(1 = yes, 0 = no) bit 4 queued erase supported(1 = yes, 0 = no) bit 5 instant individual block locking supported(1 = yes, 0 = no) bit 6 protection bits supported(1 = yes, 0 = no) bit 7 page mode read supported(1 = yes, 0 = no) bit 8 synchronous read supported(1 = yes, 0 = no) bit 9 simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional feat ures follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? ye s (p+a)h = 114h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are ?0? ye s ye s (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9v
common flash interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 86/111 table 47. protection register information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+ 11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16 table 48. burst read information offset data desc ription value (p+1d)h = 127h 0003h page-mode read capability bits 0-7 n? such that 2 n hex value represents the number of read-page bytes. see offset 0028h for device word width to determine page-mode data output width. 8 bytes (p+1e)h = 128h 0004h number of synchronous mode read configuration fields that follow. 4 (p+1f)h = 129h 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 0028h for word width to determine the burst data output width. 4 (p+20)h = 12ah 0002h synchronous mode read capability configuration 2 8 (p-21)h = 12bh (p+22)h = 12ch 0003h 0007h synchronous mode read ca pability configuration 3 16 synchronous mode read ca pability configuration 4 cont.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb common flash interface 87/111 table 49. bank and erase block region information (1) (2) 1. the variable p is a pointer that is defined at cfi offset 015h. 2. bank regions. there ar e two bank regions, see table 31 , table 34 , table 37 and table 40 . flash memory (top) flash memory (bottom) description offset data offset data (p+23)h = 12dh 02h (p+23)h = 12dh 02h number of bank regions within the device table 50. bank and erase block region 1 information flash memory (top) fl ash memory (bottom) description offset (1) data offset (1) data (p+24)h = 12eh 0fh (p+24)h = 12eh 01h number of identical banks within bank region 1 (p+25)h = 12fh 00h (p+25)h = 12fh 00h (p+26)h = 130h 11h (p+26)h = 130h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+27)h = 131h 00h (p+27)h = 131h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h (p+28)h = 132h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 01h (p+29)h = 133h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) (p+2a)h = 134h 07h (3) 0fh (4) (p+2a)h = 134h 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2b)h = 135h 00h (p+2b)h = 135h 00h (p+2c)h = 136h 00h (p+2c)h = 136h 80h (p+2d)h = 137h 02h (p+2d)h = 137h 00h (p+2e)h = 138h 64h (p+2e)h = 138h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+2f)h = 139h 00h (p+2f)h = 139h 00h
common flash interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 88/111 (p+30)h = 13ah 01h (p+30)h = 13ah 01h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+31)h = 13bh 03h (p+31)h = 13bh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted (5) bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+32)h = 13ch 06h (3) 0eh (4) bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+33)h = 13dh 00h (p+34)h = 13eh 00h (p+35)h = 13fh 02h (p+36)h = 140h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+37)h = 141h 00h (p+38)h = 142h 01h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+39)h = 143h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved 1. the variable p is a pointer that is defined at cfi offset 015h. 2. bank regions. there ar e two bank regions, see table 31 , table 34 , table 37 and table 40 . 3. applies to m58lr128kt/b only. 4. applies to m58lr256kt/b only. 5. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. table 50. bank and erase block region 1 information (continued) flash memory (top) fl ash memory (bottom) description offset (1) data offset (1) data
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb common flash interface 89/111 table 51. bank and erase block region 2 information flash memory (top) flash memory (bottom) description offset (1) data offset (1) data (p+32)h = 13ch 01h (p+3a)h = 144h 0fh number of identical banks within bank region 2 (p+33)h = 13dh 00h (p+3b)h = 145h 00h (p+34)h = 13eh 11h (p+3c)h = 146h 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+35)h = 13fh 00h (p+3d)h = 147h 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+36)h = 140h 00h (p+3e)h = 148h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+37)h = 141h 02h (p+3f)h = 149h 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+38)h = 142h 06h (3) 0eh (4) (p+40)h = 14ah 07h (3) 0fh (4) bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+39)h = 143h 00h (p+41)h = 14bh 00h (p+3a)h = 144h 00h (p+42)h = 14ch 00h (p+3b)h = 145h 02h (p+43)h = 14dh 02h (p+3c)h = 146h 64h (p+44)h = 14eh 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+3d)h = 147h 00h (p+45)h = 14fh 00h (p+3e)h = 148h 01h (p+46)h = 150h 01h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved
common flash interface m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 90/111 (p+3f)h = 149h 03h (p+47)h = 151h 03h bank region 2 (erase block type 1):page mode and synchronous mode capabilities (defined in ta b l e 4 8 ) bit 0: page-mode reads permitted (5) bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+40)h = 14ah 03h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+41)h = 14bh 00h (p+42)h = 14ch 80h (p+43)h = 14dh 00h (p+44)h = 14eh 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+45)h = 14fh 00h (p+46)h = 150h 01h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+47)h = 151h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in ta b l e 4 8 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+48)h = 152h (p+48)h = 152h feature space definitions (p+49)h = 153h (p+43)h = 153h reserved 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there ar e two bank regions, see table 31 , table 34 , table 37 and table 40 . 3. applies to m58lr128kt/b only. 4. applies to m58lr256kt/b only. 5. although the device supports page read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. table 51. bank and erase block region 2 information (continued) flash memory (top) flash memory (bottom) description offset (1) data offset (1) data
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb flowcharts and pseudocodes 91/111 appendix c flowcharts and pseudocodes figure 18. program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
flowcharts and pseudocodes m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 92/111 figure 19. blank check flowchart and pseudocode 1. any address within the bank can equally be used. 2. if an error is found, the status register must be cleared before further program/erase operations. write block address & bch start sr7 = 1 write block address & cbh read status register (1) sr4 = 1 sr5 = 1 sr5 = 0 no yes command sequence error (2) yes blank check error (2) no end blank_check_command (blocktocheck) { writetoflash (blocktocheck, 0xbc); writetoflash (blocktocheck, 0xcb); /* memory enters read status state after the blank check command */ do { status_register = readflash (blocktocheck); /* see note (1) */ /* e or g must be toggled */ } while (status_register.sr7==0); if (status_register.sr4==1) && (status_register.sr5==1) /* command sequence error */ error_handler () ; if (status_register.sr5==1) /* blank check error */ error_handler () ; } ai10520c
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb flowcharts and pseudocodes 93/111 figure 20. buffer program flowchart and pseudocode 1. n + 1 is the number of data being programmed. 2. next program data is an element belonging to buffer_progr am[].data; next program address is an element belonging to buffer_program[].address 3. routine for error check by reading sr3, sr4 and sr1. buffer program e8h command, start address ai08913b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) read status register no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /* buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { do {writetoflash ( start _address, 0xe8) ; status_register=readflash ( start _address); } while (status_register.sr7==0); writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x flowcharts and pseudocodes m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 94/111 figure 21. program suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be issu ed just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb flowcharts and pseudocodes 95/111 figure 22. block erase flowchart and pseudocode 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 20h (2) ai10976 start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
flowcharts and pseudocodes m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 96/111 figure 23. erase suspend and resume flowchart and pseudocode 1. the read status register command (write 70h) can be is sued just before or just after the erase resume command. write 70h ai13893 read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write d0h read data from another block, program, set configuration register or block protect/unprotect/lock start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ } }
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb flowcharts and pseudocodes 97/111 figure 24. locking operations flowchart and pseudocode 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai06176b read block lock states yes no locking change confirmed? start write 60h (1) locking_operation_command (address, lock_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
flowcharts and pseudocodes m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 98/111 figure 25. protection register program flowchart and pseudocode 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program erro r) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cl eared before further program/er ase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb flowcharts and pseudocodes 99/111 figure 26. buffer enhanced factory program flowchart and pseudocode write 80h to address wa1 ai07302a start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes sr4 = 1 no no no no setup phase program and verify phase exit phase buffer_enhanced_factory_program_command (start_address, dataflow[]) { writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do { do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) error_handler ( ) ;/*v pp error */ if (status_register.sr1==1) error_handler ( ) ;/* locked block * / } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<32) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); }
command interface state tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 100/111 appendix d command interface state tables table 52. command interface states - modify table, next state (1) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unlock confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h) ready ready program setup bp setup erase setup befp setup blank check setup ready lock/cr setup ready (lock error) ready (unlock block) ready (lock error) otp setup otp busy busy otp busy is in otp busy otp busy is in otp busy otp busy is in otp busy otp busy program setup program busy busy program busy is in program busy program busy is in program busy program busy program suspend program busy is in program busy program busy suspend ps is in ps ps is in program suspend ps program busy program suspend is in ps program suspend buffer program setup buffer program load 1 (give word count load (n-1)); buffer load 1 if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 (data load) buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) bp busy ready (error) busy bp busy is in bp busy bp busy is in bp busy bp busy bp suspend buffer program busy is in bp busy buffer program busy suspend bp suspend is in bp suspend bp suspend is in bp suspend bp suspend bp busy buffer program suspend is in bp suspend buffer program suspend
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface state tables 101/111 erase setup ready (error) erase busy ready (error) busy erase busy is in erase busy erase busy is in erase busy erase busy erase suspend erase busy is in erase busy erase busy suspend erase suspend program in es bp in es is in erase suspend es erase busy erase suspend is in es erase suspend program in erase suspend setup program busy in erase suspend busy program busy in es is in program busy in es program busy in es is in program busy in es program busy in es ps in es program busy in erase suspend is in program busy in es program busy in erase suspend suspend ps in es is in ps in es ps in es is in program suspend in es ps in es program busy in es program suspend in erase suspend is in ps in es program suspend in erase suspend buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)); if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 buffer load 1 buffer program load 2 in erase suspend (data load) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm erase suspend (sequence error) bp busy in es erase suspend (sequence error) busy bp busy in es is in bp busy in es bp busy in es is in bp busy in es bp busy in es bp suspend in es buffer program busy in es is in bp busy in es buffer program busy in erase suspend suspend bp suspend in es is in bp suspend in es bp suspend in es is in bp suspend in erase suspend bp suspend in es bp busy in erase suspend buffer program suspend in erase suspend is in bp suspend in es bp suspend in erase suspend table 52. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unlock confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h)
command interface state tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 102/111 blank check setup ready (error) blank check busy ready (error) busy blank check busy is in blank check busy blank check busy is in blank check busy blank check busy lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) buffer efp setup ready (error) befp busy ready (error) busy befp busy (6) 1. ci = command interface, cr = configuration register, bef p = buffer enhanced factory program, p/e c = program/erase controller, is = illegal state, bp = buffer program, es = erase suspend. 2. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 3. the two cycle command should be issued to the same bank address. 4. if the p/e c is active, both cycles are ignored. 5. the clear status register command clears the sr erro r bits except when the p/e c. is busy or suspended. 6. befp is allowed only when status register bi t sr0 is reset to '0'. befp is busy if block address is first befp address. any other commands are treated as data. table 52. command interface states - modify table, next state (1) (continued) current ci state command input read array (2) (ffh) program setup (3)(4) (10/40h) buffer program (3)(4) (e8h) block erase, setup (3)(4) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unlock confirm, befp confirm (3)(4) (d0h) blank check confirm (cbh) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature , read cfi query (90h, 98h)
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface state tables 103/111 table 53. command interface states - modify table, next output state (1) (2) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4) (5) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unlock confirm, befp confirm (4)(5) (d0h) blank check confir m (cbh) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup otp setup program setup in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend blank check setup lock/cr setup lock/cr setup in erase suspend
command interface state tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 104/111 otp busy array status register output unchanged status register output unchanged status register ready electronic signature/ cfi program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend blank check busy illegal state output unchanged 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 3. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 4. the two cycle command should be issued to the same bank address. 5. if the p/ec is active, both cycles are ignored. table 53. command interface states - modify table, next output state (1) (2) (continued) current ci state command input read array (3) (ffh) program setup (4) (5) (10/40h) buffer program (e8h) block erase, setup (4) (5) (20h) befp setup (80h) blank check setup (bch) erase confirm p/e resume, block unlock confirm, befp confirm (4)(5) (d0h) blank check confir m (cbh) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h)
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface state tables 105/111 table 54. command interface states - lock table, next state (1) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) p/e c operation completed (5) ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy is in otp busy otp busy ready is in otp busy otp busy is ready program setup program busy n/a busy is in program busy program busy ready is in program busy program busy is ready suspend is in ps program suspend n/a is in ps program suspend buffer program setup buffer program load 1 (give word count load (n-1)); n/a buffer load 1 buffer program load 2 (6) exit see note (6) n/a buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) n/a confirm ready (error) n/a busy is in bp busy buffer program busy ready is in buffer program busy buffer program busy is ready suspend is in bp suspend buffer program suspend n/a is in bp suspend buffer program suspend erase setup ready (error) n/a busy is in erase busy erase busy ready is in erase busy erase busy is ready suspend lock/cr setup in es is in es erase suspend n/a is in es erase suspend
command interface state tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 106/111 program in erase suspend setup program busy in erase suspend n/a busy is in program busy in es program busy in erase suspend es is in program busy in es program busy in erase suspend is in es suspend is in ps in es program suspend in erase suspend n/a is in ps in es program suspend in erase suspend buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)) n/a buffer load 1 buffer program load 2 in erase suspend (7) exit see note (7) buffer load 2 buffer program confirm in erase suspend when c ount =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm erase suspend (sequence error) busy is in bp busy in es buffer program busy in erase suspend es is in bp busy in es bp busy in es is in es suspend is in bp suspend in es buffer program suspend in erase suspend n/a is in bp suspend in es buffer program suspend in erase suspend blank check setup ready (error) n/a blank check busy is in blank check busy blank check busy ready lock/cr setup in es erase suspend (lock error) erase suspend erase suspend (lock error) n/a befp setup ready (error) n/a busy befp busy (8) exit befp busy (8) n/a 1. ci = command interface, cr = configuration register, bef p = buffer enhanced factory program, p/e c = program/erase controller, is = illegal state, bp = buffer program, es = erase suspend, wa0 = address in a block different from first befp address. 2. if the p/e c is active, both cycle are ignored. 3. befp exit when block address is different from first block address and data are ffffh. 4. illegal commands are those not defined in the command set. 5. n/a: not available. in this case the state remains unchanged. 6. if n=0 go to buffer program confirm. else (not =0) go to buffer program load 2 (data load) 7. if n=0 go to buffer program confirm in erase suspend. else (not =0) go to buffer program load 2 in erase suspend. 8. befp is allowed only when status register bit sr0 is set to '0'. befp is busy if block addr ess is first befp address. any other commands are treated as data. table 54. command interface states - lock table, next state (1) (continued) current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (4) p/e c operation completed (5)
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb command interface state tables 107/111 table 55. command interface states - lock table, next output state (1) (2) current ci state command input lock/cr setup (3) ( 60h) blank check setup (bch) otp setup (3) (c0h) blank check confirm (cbh) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) p. e./c. operation completed program setup status register output unchanged erase setup otp setup program setup in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend blank check setup lock/cr setup status register array status register lock/cr setup in erase suspend
command interface state tables m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 108/111 otp busy status register output unchanged array output unchanged ready program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend blank check busy illegal state output unchanged 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank's output state. 2. ci = command interface, cr = configuration register , befp = buffer enhanced factory program, p/e. c. = program/erase controller. 3. if the p/ec is active, both cycles are ignored. 4. befp exit when block address is different from first block address and data are ffffh. 5. illegal commands are those not defined in the command set. table 55. command interface states - lock table, next output state (continued) (1) (2) current ci state command input lock/cr setup (3) ( 60h) blank check setup (bch) otp setup (3) (c0h) blank check confirm (cbh) block lock confirm (01h) block lock- down confirm (2fh) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) p. e./c. operation completed
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb revision history 109/111 14 revision history table 56. document revision history date revision changes 23-mar-2007 1 initial release. 06-dec-2007 2 in table 18: program/erase times and endurance cycles , changed the suspend latency program and erase values to 5, 10 and 5, 20 respectively, to 20 and 25 for both. in table 19: absolute maximum ratings , changed the v io maximum value from 3.8 to v ddq + 0.6 v. in table 22: dc characteristics - currents : ? added the 256 mbit values for i dd2 , i dd3 , and i dd7 . ?for i dd5 , changed the supply current (both program and erase) v pph values to 10 and 30, and changed the v dd and values to 20 and 35, respectively. ?for i dd6 , changed the ?asynchronous read in another bank? values to 33 and 50, respectively; changed the ?synchronous read in another bank? values to 50 and 67, respectively. in table 28: reset and power-up ac characteristics , changed the t vdhph value from 250 to 300. 27-mar-2008 3 applied numonyx branding.
m58lr128kt, m58lr128kb, m58lr256kt, m58lr256kb 110/110 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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